Processing-in-Memory (PIM) (48 formal, 16 CCF-A)
存算一体架构：ReRAM/SRAM/DRAM 加速器、in-memory search、crossbar 设计
1. Yilong Zhao, Fangxin Liu, Zongwu Wang, Mingjian Li, Mingxing Zhang, Chixiao Chen, and
Li Jiang*, “BLADE: Boosting LLM Decoding's Communication Efficiency in DRAM-based PIM.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
CCF-C [DBLP] [Scholar]
2. Haomin Li, Fangxin Liu, Chenyang Guan, Zongwu Wang,
Li Jiang*, and Haibing Guan, “LaMoS: Enabling Efficient Large Number Modular Multiplication through SRAM-based CiM Acceleration.”,
Design, Automation and Test in Europe Conference (DATE), 2026.
CCF-B CSRankings [DBLP] [Scholar]
3. Jiahao Sun, Yijian Zhang, Yuzhuo Liu, Fangxin Liu, Li Jiang, and Rui Yang, “A Sub- 10 μs In-Memory-Search Collision Detection Accelerator Based on RRAM-TCAMs.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2025.
CCF-A [DBLP] [Scholar]
4. Fangxin Liu, Zongwu Wang, Peng Xu, Shiyuan Huang, and
Li Jiang*, “Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.
CCF-C [DBLP] [Scholar]
5. Fangxin Liu, Zongwu Wang, Ning Yang, Haomin Li, Tao Yang, Haibing Guan, and
Li Jiang*, “Irregular Sparsity-Enabled Search-in-Memory Engine for Accelerating Spiking Neural Networks.”,
Asian Conference on Parallel and Distributed Technology (APPT), 2025.
[DBLP] [Scholar]
6. Yiwei Hu, Fangxin Liu, Zongwu Wang, Yilong Zhao, Tao Yang, Li Jiang, and Haibing Guan, “PLAIN: Leveraging High Internal Bandwidth in PIM for Accelerating Large Language Model Inference via Mixed-Precision Quantization.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025.
CCF-B CSRankings [DBLP] [Scholar]
7. Yilong Zhao, Fangxin Liu, Mingyu Gao, Xiaoyao Liang, Qidong Tang, Chengyang Gu, Tao Yang, Naifeng Jing, and
Li Jiang*, “STAMP: Accelerating Second-Order DNN Training Via ReRAM-Based Processing-in-Memory Architecture.”,
Asian Conference on Parallel and Distributed Technology (APPT), 2025.
[DBLP] [Scholar]
8. Zongwu Wang, Fangxin Liu, Ning Yang, Shiyuan Huang, Haomin Li, and
Li Jiang*, “COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with Adaptive Spike Speculation.”,
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024.
CCF-A CSRankings [DBLP] [Scholar]
9. Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Xiaoyao Liang, and
Li Jiang*, “ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity.”,
IEEE Transactions on Computers (IEEE TC), 2024.
CCF-A [DBLP] [Scholar]
10. Fangxin Liu, Shiyuan Huang, Longyu Zhao,
Li Jiang*, and Zongwu Wang, “LowPASS: A Low power PIM-based accelerator with Speculative Scheme for SNNs.”,
International Symposium on Low Power Electronics and Design (ISLPED), 2024.
CCF-C [DBLP] [Scholar]
11. Boyu Tian, Yiwei Li, Li Jiang, Shuangyu Cai, and Mingyu Gao, “NDPBridge: Enabling Cross-Bank Coordination in Near-DRAM-Bank Processing Architectures.”,
International Symposium on Computer Architecture (ISCA), 2024.
CCF-A CSRankings [DBLP] [Scholar]
12. Fangxin Liu, Haomin Li, Ning Yang, Yichi Chen, Zongwu Wang, Tao Yang, and
Li Jiang*, “PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
CCF-C [DBLP] [Scholar]
13. Jiahao Sun, Fangxin Liu, Yijian Zhang, Li Jiang, and Rui Yang, “RTSA: An RRAM-TCAM based In-Memory-Search Accelerator for Sub-100 µs Collision Detection.”,
Design, Automation and Test in Europe Conference (DATE), 2024.
CCF-B CSRankings [DBLP] [Scholar]
14. Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, and
Li Jiang*, “UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space.”,
International Symposium on Computer Architecture (ISCA), 2024.
CCF-A CSRankings [DBLP] [Scholar]
15. Chen Nie, Chenyu Tang, Jie Lin, Huan Hu, Chenyang Lv, Ting Cao, Weifeng Zhang, Li Jiang, Xiaoyao Liang, Weikang Qian, Yanan Sun, and Zhezhi He, “VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations.”,
IEEE Transactions on Computers (IEEE TC), 2024.
CCF-A [DBLP] [Scholar]
16. Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, and Xiaoyao Liang, “Watt: A Write-Optimized RRAM-Based Accelerator for Attention.”,
EURO-PAR: International Conference on Parallel and Distributed Computing (Euro-Par), 2024.
[DBLP] [Scholar]
17. Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, and Xiaoyao Liang, “HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model.”,
IEEE International Conference on Computer Design (ICCD), 2023.
CCF-B [DBLP] [Scholar]
18. Tao Yang, Dongyue Li, Fei Ma, Zhuoran Song, Yilong Zhao, Jiaxi Zhang, Fangxin Liu, and
Li Jiang*, “PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2023.
CCF-A [DBLP] [Scholar]
19. Tao Yang, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun, and
Li Jiang*, “PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy.”,
Design, Automation and Test in Europe Conference (DATE), 2023.
CCF-B CSRankings [DBLP] [Scholar]
20. Fangxin Liu, Ning Yang, and
Li Jiang*, “PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-based Architecture.”,
IEEE International Conference on Computer Design (ICCD), 2023.
CCF-B [DBLP] [Scholar]
21. Fangxin Liu, Wenbo Zhao, Zongwu Wang, Xiaokang Yang, and
Li Jiang*, “SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN Acceleration.”,
Design, Automation and Test in Europe Conference (DATE), 2023.
CCF-B CSRankings [DBLP] [Scholar]
22. Fangxin Liu, Zongwu Wang, Yongbiao Chen, Zhezhi He, Tao Yang, Xiaoyao Liang, and
Li Jiang*, “SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2023.
CCF-A [DBLP] [Scholar]
23. Chen Nie, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang, and Zhezhi He, “Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System.”,
International Symposium on Quality Electronic Design (ISQED), 2022.
[DBLP] [Scholar]
24. Qidong Tang, Zhezhi He, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, and
Li Jiang*, “HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2022.
CCF-C [DBLP] [Scholar]
25. Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yilong Zhao, Tao Yang, Yiran Chen, and
Li Jiang*, “IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2022.
CCF-A [DBLP] [Scholar]
26. Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, and Li Jiang, “Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals.”,
IEEE Transactions on Computers (IEEE TC), 2022.
CCF-A [DBLP] [Scholar]
27. Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Zhezhi He, Rui Yang, Qidong Tang, Tao Yang, Cheng Zhuo, and
Li Jiang*, “PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration.”,
Design Automation Conference (DAC), 2022.
CCF-A CSRankings [DBLP] [Scholar]
28. Zongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, and
Li Jiang*, “Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing.”,
Design, Automation and Test in Europe Conference (DATE), 2022.
CCF-B CSRankings [DBLP] [Scholar]
29. Tianhong Shen, Yanan Sun, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, and Li Jiang, “A Ternary Memristive Logic-in-Memory Design for Fast Data Scan.”,
International Conference on IC Design and Technology (ICTA), 2021.
[DBLP] [Scholar]
30. Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, and
Li Jiang*, “Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021.
CCF-B CSRankings [DBLP] [Scholar]
31. Ziqi Meng, Weikang Qian, Yilong Zhao, Yanan Sun, Rui Yang, and Li Jiang, “Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation.”,
Design, Automation and Test in Europe Conference (DATE), 2021.
CCF-B CSRankings [DBLP] [Scholar]
32. Hongtao Zhong, Shengjie Cao, Li Jiang, Xia An, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, and Xueqing Li, “DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.”,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2021.
CCF-B [DBLP] [Scholar]
33. Chen Nie, Jie Lin, Huan Hu, Li Jiang, Xiaoyao Liang, and Zhezhi He, “Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support.”,
ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021.
CCF-C [DBLP] [Scholar]
34. Fangxin Liu, Wenbo Zhao, Zongwu Wang, Tao Yang, and
Li Jiang*, “IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration.”,
ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021.
CCF-C [DBLP] [Scholar]
35. Zhuoran Song, Yanan Sun, Lerong Chen, Tianjian Li, Naifeng Jing, Xiaoyao Liang, and
Li Jiang*, “ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2021.
CCF-A [DBLP] [Scholar]
36. Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, and
Li Jiang*, “PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration.”,
Design Automation Conference (DAC), 2021.
CCF-A CSRankings [DBLP] [Scholar]
37. Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and
Li Jiang*, “Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.”,
ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021.
CCF-C [DBLP] [Scholar]
38. Zhuoran Song, Dongyue Li, Zhezhi He, Xiaoyao Liang, and
Li Jiang*, “ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator.”,
IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
CCF-B [DBLP] [Scholar]
39. Fangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Tao Yang, Jingnai Feng, Xiaoyao Liang, and
Li Jiang*, “SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.”,
IEEE International Conference on Computer Design (ICCD), 2021.
CCF-B [DBLP] [Scholar]
40. Yanan Sun, Chang Ma, Zhi Li, Yilong Zhao, Jiachen Jiang, Weikang Qian, Rui Yang, Zhezhi He, and Li Jiang, “Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2021.
CCF-A [DBLP] [Scholar]
41. Zhuoran Song, Yilong Zhao, Yanan Sun, Xiaoyao Liang, and
Li Jiang*, “ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory.”,
ACM Great Lakes Symposium on VLSI (GLSVLSI), 2020.
CCF-C [DBLP] [Scholar]
42. Chang Ma, Yanan Sun, Weikang Qian, Ziqi Meng, Rui Yang, and Li Jiang, “Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing.”,
Design, Automation and Test in Europe Conference (DATE), 2020.
CCF-B CSRankings [DBLP] [Scholar]
43. Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, and
Li Jiang*, “PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture.”,
Design Automation Conference (DAC), 2020.
CCF-A CSRankings [DBLP] [Scholar]
44. Geng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, and Yanzhi Wang, “An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM.”,
International Symposium on Low Power Electronics and Design (ISLPED), 2019.
CCF-C [DBLP] [Scholar]
45. Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, and Li Jiang, “Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.”,
IEEE Transactions on Circuits and Systems II: Express Briefs (IEEE TCAS-II), 2019.
[DBLP] [Scholar]
46. Houxiang Ji, Linghao Song, Li Jiang, Hai Helen Li, and Yiran Chen, “ReCom: An efficient resistive accelerator for compressed deep neural networks.”,
Design, Automation and Test in Europe Conference (DATE), 2018.
CCF-B CSRankings [DBLP] [Scholar]
47. Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang, and Li Jiang, “Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.”,
Design, Automation and Test in Europe Conference (DATE), 2017.
CCF-B CSRankings [DBLP] [Scholar]
48. Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, and Li Jiang, “Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique.”,
Design Automation Conference (DAC), 2017.
CCF-A CSRankings [DBLP] [Scholar]
49. Yilong Zhao, Fangxin Liu, Onur Mutlu, Mingyu Gao, Jian Liu, Haibing Guan, and
Li Jiang*, “COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices.”,
arXiv (CoRR), 2026.
arXiv[DBLP] [Scholar]
50. Haomin Li, Fangxin Liu, Chenyang Guan, Zongwu Wang,
Li Jiang*, and Haibing Guan, “LaMoS: Enabling Efficient Large Number Modular Multiplication through SRAM-based CiM Acceleration.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
51. Yilong Zhao, Mingyu Gao, Huanchen Zhang, Fangxin Liu, Gongye Chen, He Xian, Haibing Guan, and
Li Jiang*, “PUSHtap: PIM-based In-Memory HTAP with Unified Data Storage Format.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
52. Weidong Cao, Yilong Zhao, Adith Boloor, Yinhe Han, Xuan Zhang, and Li Jiang, “Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals.”,
arXiv (CoRR), 2022.
arXiv[DBLP] [Scholar]
53. Yilong Zhao, Li Jiang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Fangxin Liu, Tao Yang, and Xiaoyao Liang, “RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN.”,
arXiv (CoRR), 2022.
arXiv[DBLP] [Scholar]
54. Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and
Li Jiang*, “SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.”,
arXiv (CoRR), 2021.
arXiv[DBLP] [Scholar]
55. Geng Yuan, Xiaolong Ma, Caiwen Ding, Sheng Lin, Tianyun Zhang, Zeinab S. Jalali, Yilong Zhao, Li Jiang, Sucheta Soundarajan, and Yanzhi Wang, “An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM.”,
arXiv (CoRR), 2019.
arXiv[DBLP] [Scholar]
LLM Systems & Efficient Inference (16 formal, 6 CCF-A)
大模型推理：KV-cache 压缩、量化、MoE 加速、speculative decoding
1. Fangxin Liu, Ning Yang, Jingkui Yang, Zongwu Wang, Chenyang Guan, Yu Feng,
Li Jiang*, and Haibing Guan, “EARTH: An Efficient MoE Accelerator with Entropy-Aware Speculative Prefetch and Result Reuse.”,
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2026.
CCF-A [DBLP] [Scholar]
2. Zhixiong Zhao, Fangxin Liu, Junjie Wang, Chenyang Guan, Zongwu Wang, Li Jiang, and Haibing Guan, “SpecQuant: Spectral Decomposition and Adaptive Truncation for Ultra-Low-Bit LLMs Quantization.”,
AAAI Conference on Artificial Intelligence (AAAI), 2026.
CCF-A CSRankings [DBLP] [Scholar]
3. Zongwu Wang, Zhongyi Tang, Fangxin Liu, Chenyang Guan,
Li Jiang*, and Haibing Guan, “TFLOP: Towards Energy-Efficient LLM Inference An FPGA-Affinity Accelerator with Unified LUT-based OPtimization.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
CCF-C [DBLP] [Scholar]
4. Junjie Wang, Fangxin Liu, Jinqi Zhu, Chenyang Guan, Tao Yang,
Li Jiang*, and Haibing Guan, “When Low-Rank Meets Mixed-Precision: Training-Free Joint Compression for Efficient LLM Inference.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
CCF-C [DBLP] [Scholar]
5. Fangxin Liu, Haomin Li, Zongwu Wang, Bo Zhang, Mingzhe Zhang, Shoumeng Yan,
Li Jiang*, and Haibing Guan, “ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid Workloads.”,
Design Automation Conference (DAC), 2025.
CCF-A CSRankings [DBLP] [Scholar]
6. Fangxin Liu, Junjie Wang, Ning Yang, Zongwu Wang, Junping Zhao,
Li Jiang*, and Haibing Guan, “ASTER: Adaptive Dynamic Layer-Skipping for Efficient Transformer Inference via Markov Decision Process.”,
ACM International Conference on Multimedia (ACM MM), 2025.
[DBLP] [Scholar]
7. Zongwu Wang, Fangxin Liu, Peng Xu, Qingxiao Sun, Junping Zhao, and
Li Jiang*, “EVASION: Efficient KV CAche CompreSsion vIa PrOduct QuaNtization.”,
Design, Automation and Test in Europe Conference (DATE), 2025.
CCF-B CSRankings [DBLP] [Scholar]
8. Fangxin Liu, Zongwu Wang, JinHong Xia, Junping Zhao, Shouren Zhao, Jinjin Li, Jian Liu,
Li Jiang*, and Haibing Guan, “FlexQuant: A Flexible and Efficient Dynamic Precision Switching Framework for LLM Quantization.”,
Conference on Empirical Methods in Natural Language Processing (EMNLP, Findings), 2025.
CCF-B [DBLP] [Scholar]
9. Zongwu Wang, Peng Xu, Fangxin Liu, Yiwei Hu, Qingxiao Sun, Gezi Li, Cheng Li, Xuan Wang,
Li Jiang*, and Haibing Guan, “MILLION: MasterIng Long-Context LLM Inference Via Outlier-Immunized KV Product QuaNtization.”,
Design Automation Conference (DAC), 2025.
CCF-A CSRankings [DBLP] [Scholar]
10. Fangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, Qi Sun, and
Li Jiang*, “OPS: Outlier-Aware Precision-Slice Framework for LLM Acceleration.”,
Design, Automation and Test in Europe Conference (DATE), 2025.
CCF-B CSRankings [DBLP] [Scholar]
11. Zhixiong Zhao, Haomin Li, Fangxin Liu, Yuncheng Lu, Zongwu Wang, Tao Yang, Li Jiang, and Haibing Guan, “QUARK: Quantization-Enabled Circuit Sharing for Transformer Acceleration by Exploiting Common Patterns in Nonlinear Operations.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025.
CCF-B CSRankings [DBLP] [Scholar]
12. Xuhang Wang, Zhuoran Song, Chunyu Qi, Fangxin Liu, Naifeng Jing, Li Jiang, and Xiaoyao Liang, “RTSA: A Run-Through Sparse Attention Framework for Video Transformer.”,
IEEE Transactions on Computers (IEEE TC), 2025.
CCF-A [DBLP] [Scholar]
13. Fangxin Liu, Ning Yang, Zhiyan Song, Zongwu Wang, and
Li Jiang*, “HOLES: Boosting Large Language Models Efficiency with Hardware-Friendly Lossless Encoding.”,
IEEE International Conference on Computer Design (ICCD), 2024.
CCF-B [DBLP] [Scholar]
14. Zongwu Wang, Fangxin Liu, Xin Tang, and
Li Jiang*, “PS4: A Low Power SNN Accelerator with Spike Speculative Scheme.”,
IEEE International Conference on Computer Design (ICCD), 2024.
CCF-B [DBLP] [Scholar]
15. Tao Yang, Fei Ma, Xiaoling Li, Fangxin Liu, Yilong Zhao, Zhezhi He, and
Li Jiang*, “DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2023.
CCF-A [DBLP] [Scholar]
16. Tao Yang, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, and
Li Jiang*, “DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture.”,
Design, Automation and Test in Europe Conference (DATE), 2022.
CCF-B CSRankings [DBLP] [Scholar]
17. Fangxin Liu, Qinghua Zhang, Hanjing Shen, Zhibo Liang, Li Jiang, Haibing Guan, Chong Bao, and Xuefeng Jin, “HyperOffload: Graph-Driven Hierarchical Memory Management for Large Language Models on SuperNode Architectures.”,
arXiv (CoRR), 2026.
arXiv[DBLP] [Scholar]
18. Fangxin Liu, Haomin Li, Zongwu Wang, Bo Zhang, Mingzhe Zhang, Shoumeng Yan,
Li Jiang*, and Haibing Guan, “ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid Workloads.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
19. Ning Yang, Fangxin Liu, Junjie Wang, Tao Yang, Kang Liu, Haibing Guan, and
Li Jiang*, “DASH: Input-Aware Dynamic Layer Skipping for Efficient LLM Inference with Markov Decision Policies.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
20. Fangxin Liu, Zongwu Wang, JinHong Xia, Junping Zhao, Jian Liu, Haibing Guan, and
Li Jiang*, “FlexQuant: A Flexible and Efficient Dynamic Precision Switching Framework for LLM Quantization.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
21. Fangxin Liu, Ning Yang, Junping Zhao, Tao Yang, Haibing Guan, and
Li Jiang*, “LCD: Advancing Extreme Low-Bit Clustering for Large Language Models via Knowledge Distillation.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
22. Zongwu Wang, Peng Xu, Fangxin Liu, Yiwei Hu, Qingxiao Sun, Gezi Li, Cheng Li, Xuan Wang,
Li Jiang*, and Haibing Guan, “MILLION: Mastering Long-Context LLM Inference Via Outlier-Immunized KV Product Quantization.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
23. Zhixiong Zhao, Haomin Li, Fangxin Liu, Yuncheng Lu, Zongwu Wang, Tao Yang, Li Jiang, and Haibing Guan, “QUARK: Quantization-Enabled Circuit Sharing for Transformer Acceleration by Exploiting Common Patterns in Nonlinear Operations.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
24. Zhixiong Zhao, Fangxin Liu, Junjie Wang, Chenyang Guan, Zongwu Wang, Li Jiang, and Haibing Guan, “SpecQuant: Spectral Decomposition and Adaptive Truncation for Ultra-Low-Bit LLMs Quantization.”,
arXiv (CoRR), 2025.
arXiv[DBLP] [Scholar]
25. Zongwu Wang, Fangxin Liu, Mingshuai Li, and
Li Jiang*, “TokenRing: An Efficient Parallelism Framework for Infinite-Context LLMs via Bidirectional Communication.”,
arXiv (CoRR), 2024.
arXiv[DBLP] [Scholar]
26. Zhuoran Song, Yihong Xu, Zhezhi He, Li Jiang, Naifeng Jing, and Xiaoyao Liang, “CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction.”,
arXiv (CoRR), 2022.
arXiv[DBLP] [Scholar]
AI Accelerators & Parallel Architecture (24 formal, 7 CCF-A)
AI 加速器与并行架构：GPGPU、SIMD、近似计算、FPGA 异构
1. Longyu Zhao, Zongwu Wang, Fangxin Liu, and
Li Jiang*, “Ninja: A Hardware Assisted System for Accelerating Nested Address Translation.”,
IEEE International Conference on Computer Design (ICCD), 2024.
CCF-B [DBLP] [Scholar]
2. Yaoyao Ye, Zixuan Liu, Jungan Liu, and Li Jiang, “ASDR: An Application-Specific Deadlock-Free Routing for Chiplet-Based Systems.”,
Workshop on Network-on-Chip Architectures (NoCArc@MICRO), 2023.
[DBLP] [Scholar]
3. Yu Gong, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, and Li Jiang, “N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.”,
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2022.
CCF-B CSRankings [DBLP] [Scholar]
4. Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, and Naifeng Jing, “A sharing-aware L1.5D cache for data reuse in GPGPUs.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2019.
CCF-C [DBLP] [Scholar]
5. Zhuoran Song, Ru Wang, Dongyu Ru, Zhenghao Peng, Hongru Huang, Hai Zhao, Xiaoyao Liang, and
Li Jiang*, “Approximate Random Dropout for DNN training acceleration in GPGPU.”,
Design, Automation and Test in Europe Conference (DATE), 2019.
CCF-B CSRankings [DBLP] [Scholar]
6. Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing, Weifeng Zhang, and Xiaoyao Liang, “Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method.”,
ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), 2019.
CCF-B [DBLP] [Scholar]
7. Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, and Li Jiang, “A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).”,
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2018.
CCF-B CSRankings [DBLP] [Scholar]
8. Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, and Li Jiang, “AXNet: approximate computing using an end-to-end trainable neural network.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018.
CCF-B CSRankings [DBLP] [Scholar]
9. Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, and Xiaoyao Liang, “CNFET-Based High Throughput SIMD Architecture.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2018.
CCF-A [DBLP] [Scholar]
10. Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, and Naifeng Jing, “IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.”,
IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 2018.
CCF-A [DBLP] [Scholar]
11. Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, and Li Jiang, “Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018.
CCF-B CSRankings [DBLP] [Scholar]
12. Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, and Xiaoyao Liang, “Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.”,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2017.
CCF-B [DBLP] [Scholar]
13. Jianfei Wang, Fengfeng Fan, Li Jiang, Xiaoyao Liang, and Naifeng Jing, “Incorporating selective victim cache into GPGPU for high-performance computing.”,
Concurrency and Computation: Practice and Experience, 2017.
[DBLP] [Scholar]
14. Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, and Li Jiang, “On Quality Trade-off Control for Approximate Computing Using Iterative Training.”,
Design Automation Conference (DAC), 2017.
CCF-A CSRankings [DBLP] [Scholar]
15. Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, and Li Jiang, “A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2016.
CCF-A [DBLP] [Scholar]
16. Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang, and Naifeng Jing, “Applying Victim Cache in High Performance GPGPU Computing.”,
International Symposium on Parallel and Distributed Computing (ISPDC), 2016.
[DBLP] [Scholar]
17. Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, and Xiaoyao Liang, “CNFET-based high throughput register file architecture.”,
IEEE International Conference on Computer Design (ICCD), 2016.
CCF-B [DBLP] [Scholar]
18. Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, and Xiaoyao Liang, “Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs.”,
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016.
CCF-A CSRankings [DBLP] [Scholar]
19. Tianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu, and Krishnendu Chakrabarty, “Defect tolerance for CNFET-based SRAMs.”,
IEEE International Test Conference (ITC), 2016.
CCF-B CSRankings [DBLP] [Scholar]
20. Naifeng Jing, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, and Xiaoyao Liang, “Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.”,
IEEE Transactions on Computers (IEEE TC), 2016.
CCF-A [DBLP] [Scholar]
21. Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, and Xiaoyao Liang, “Bank stealing for conflict mitigation in GPGPU Register File.”,
International Symposium on Low Power Electronics and Design (ISLPED), 2015.
CCF-C [DBLP] [Scholar]
22. Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, and Li Jiang, “Jump test for metallic CNTs in CNFET-based SRAM.”,
Design Automation Conference (DAC), 2015.
CCF-A CSRankings [DBLP] [Scholar]
23. Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, and Li Jiang, “On microarchitectural modeling for CNFET-based circuits.”,
IEEE/ACM International Symposium on System-on-Chip (SoC), 2015.
CSRankings [DBLP] [Scholar]
24. Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, and Weikang Qian, “Timing-driven placement for carbon nanotube circuits.”,
IEEE/ACM International Symposium on System-on-Chip (SoC), 2015.
CSRankings [DBLP] [Scholar]
25. Xiangyu Wen, Yuang Zhao, Xiaoyu Xu, Lingjun Chen, Changran Xu, Shu Chi, Jianrong Ding, Zeju Li, Haomin Li, Li Jiang, Fangxin Liu, and Qiang Xu, “From Craft to Kernel: A Governance-First Execution Architecture and Semantic ISA for Agentic Computers.”,
arXiv (CoRR), 2026.
arXiv[DBLP] [Scholar]
26. Yu Gong, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, and Li Jiang, “N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.”,
arXiv (CoRR), 2021.
arXiv[DBLP] [Scholar]
27. Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, and Li Jiang, “AXNet: ApproXimate computing using an end-to-end trainable neural network.”,
arXiv (CoRR), 2018.
arXiv[DBLP] [Scholar]
28. Zhuoran Song, Dongyu Ru, Ru Wang, Hongru Huang, Zhenghao Peng, Jing Ke, Xiaoyao Liang, and
Li Jiang*, “Approximate Random Dropout.”,
arXiv (CoRR), 2018.
arXiv[DBLP] [Scholar]
29. Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, and Li Jiang, “Invocation-driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators.”,
arXiv (CoRR), 2018.
arXiv[DBLP] [Scholar]
Model Compression, Quantization & Sparsity (20 formal, 10 CCF-A)
模型压缩/量化/稀疏：低比特、剪枝、bit-slice、数据无关量化
1. Junjie Wang, Can Cui, Fangxin Liu,
Li Jiang*, and Haibing Guan, “DNA-ViT: Developmental Neural Archiving for Storage-Efficient Vision Transformers.”,
ACM International Conference on Multimedia (ACM MM), 2026.
[Paper] [Scholar] [Demo]
2. Fangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong,
Li Jiang*, and Haibing Guan, “BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision.”,
Design Automation Conference (DAC), 2025.
CCF-A CSRankings [DBLP] [Scholar]
3. Fangxin Liu, Shiyuan Huang, Ning Yang, Zongwu Wang, Haomin Li, and
Li Jiang*, “CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels.”,
IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025.
CCF-A CSRankings [DBLP] [Scholar]
4. Haomin Li, Fangxin Liu, Zewen Sun, Zongwu Wang, Shiyuan Huang, Ning Yang, and
Li Jiang*, “NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.
CCF-C [DBLP] [Scholar]
5. Shiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Ning Yang, Haomin Li, and
Li Jiang*, “STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization.”,
ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), 2025.
CCF-B [DBLP] [Scholar]
6. Shiyuan Huang, Fangxin Liu, Tao Yang, Zongwu Wang, Ning Yang, and
Li Jiang*, “SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2025.
CCF-A [DBLP] [Scholar]
7. Fangxin Liu, Ning Yang, Zhiyan Song, Zongwu Wang, Haomin Li, Shiyuan Huang, Zhuoran Song, Songwen Pei, and
Li Jiang*, “INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding.”,
Design Automation Conference (DAC), 2024.
CCF-A CSRankings [DBLP] [Scholar]
8. Fangxin Liu, Ning Yang, Haomin Li, Zongwu Wang, Zhuoran Song, Songwen Pei, and
Li Jiang*, “SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding.”,
IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024.
CCF-A CSRankings [DBLP] [Scholar]
9. Ning Yang, Fangxin Liu, Zongwu Wang, Junping Zhao, and
Li Jiang*, “SearchQ: Search-Based Fine-Grained Quantization for Data-Free Model Compression.”,
IEEE Transactions on Circuits and Systems for Artificial Intelligence (IEEE TCS-AI), 2024.
[DBLP] [Scholar]
10. Ning Yang, Fangxin Liu, Zongwu Wang, Zhiyan Song, Tao Yang, and
Li Jiang*, “T-BUS: Taming Bipartite Unstructured Sparsity for Energy-Efficient DNN Acceleration.”,
IEEE International Conference on Computer Design (ICCD), 2024.
CCF-B [DBLP] [Scholar]
11. Shiyuan Huang, Fangxin Liu, Tian Li, Zongwu Wang, Haomin Li, and
Li Jiang*, “TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
CCF-C [DBLP] [Scholar]
12. Tao Yang, Yiyuan Zhou, Qidong Tang, Feng Xu, Hui Ma, Jieru Zhao, and
Li Jiang*, “SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.”,
Design Automation Conference (DAC), 2023.
CCF-A CSRankings [DBLP] [Scholar]
13. Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, and
Li Jiang*, “EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks.”,
Design Automation Conference (DAC), 2022.
CCF-A CSRankings [DBLP] [Scholar]
14. Fangxin Liu, Zongwu Wang, Wenbo Zhao, Yongbiao Chen, Tao Yang, Xiaokang Yang, and
Li Jiang*, “Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs.”,
IEEE International Conference on Computer Design (ICCD), 2022.
CCF-B [DBLP] [Scholar]
15. Dongyue Li, Tao Yang, Lun Du, Zhezhi He, and Li Jiang, “AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs.”,
ACM International Conference on Information and Knowledge Management (CIKM), 2021.
CCF-B [DBLP] [Scholar]
16. Tao Yang, Zhezhi He, Tengchuan Kou, Qingzheng Li, Qi Han, Haibao Yu, Fangxin Liu, Yun Liang, and
Li Jiang*, “BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization.”,
ACM Transactions on Reconfigurable Technology and Systems (ACM TRETS), 2021.
CCF-B [DBLP] [Scholar]
17. Fangxin Liu, Wenbo Zhao, Zhezhi He, Yanzhi Wang, Zongwu Wang, Changzhi Dai, Xiaoyao Liang, and
Li Jiang*, “Improving Neural Network Efficiency via Post-training Quantization with Adaptive Floating-Point.”,
IEEE/CVF International Conference on Computer Vision (ICCV), 2021.
CCF-A CSRankings [DBLP] [Scholar]
18. Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, and
Li Jiang*, “A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern.”,
International Conference on Field Programmable Logic and Applications (FPL), 2020.
CSRankings [DBLP] [Scholar]
19. Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, and Xiaoyao Liang, “DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration.”,
International Symposium on Computer Architecture (ISCA), 2020.
CCF-A CSRankings [DBLP] [Scholar]
20. Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, and Naifeng Jing, “GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores.”,
Design Automation Conference (DAC), 2020.
CCF-A CSRankings [DBLP] [Scholar]
21. Zhuoran Song, Yihong Xu, Han Li, Naifeng Jing, Xiaoyao Liang, and
Li Jiang*, “DNN Training Acceleration via Exploring GPGPU Friendly Sparsity.”,
arXiv (CoRR), 2022.
arXiv[DBLP] [Scholar]
22. Fangxin Liu, Wenbo Zhao, Yanzhi Wang, Changzhi Dai, and
Li Jiang*, “AUSN: Approximately Uniform Quantization by Adaptively Superimposing Non-uniform Distribution for Deep Neural Networks.”,
arXiv (CoRR), 2020.
arXiv[DBLP] [Scholar]
3D-IC / Memory Reliability (24 formal, 3 CCF-A)
3D-IC/TSV 测试修复与存储器可靠性：yield、BISR、容错
1. Hanchen Guo, Zhehan Lin, Yunfei Gu, Chentao Wu, Li Jiang, Jie Li, Guangtao Xue, and Minyi Guo, “Lazy-WL: A Wear-aware Load Balanced Data Redistribution Method for Efficient SSD Array Scaling.”,
IEEE International Conference on Cluster Computing (CLUSTER), 2021.
CSRankings [DBLP] [Scholar]
2. Xingyi Wang, Yu Li, Yiquan Chen, Shiwen Wang, Yin Du, Cheng He, Yuzhong Zhang, Pinan Chen, Xin Li, Wenjun Song, Qiang Xu, and
Li Jiang*, “On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers.”,
IEEE VLSI Test Symposium (VTS), 2021.
[DBLP] [Scholar]
3. Xingyi Wang,
Li Jiang*, and Krishnendu Chakrabarty, “LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection.”,
IEEE VLSI Test Symposium (VTS), 2020.
[DBLP] [Scholar]
4. Xiaoyi Sun, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao, Hai Cao, Yinhe Han, Xiaoyao Liang, and
Li Jiang*, “System-level hardware failure prediction using deep learning.”,
Design Automation Conference (DAC), 2019.
CCF-A CSRankings [DBLP] [Scholar]
5. Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, and Li Jiang, “In-growth test for monolithic 3D integrated SRAM.”,
Design, Automation and Test in Europe Conference (DATE), 2018.
CCF-B CSRankings [DBLP] [Scholar]
6. Chen Wang, Yanan Sun, Shiyan Hu, Li Jiang, and Weikang Qian, “Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit.”,
ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), 2018.
CCF-B [DBLP] [Scholar]
7. Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, and Li Jiang, “Fault clustering technique for 3D memory BISR.”,
Design, Automation and Test in Europe Conference (DATE), 2017.
CCF-B CSRankings [DBLP] [Scholar]
8. Xiaolong Zhang, Huiyun Li, Li Jiang, and Qiang Xu, “A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method.”,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2015.
CCF-B [DBLP] [Scholar]
9. Li Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang, and Huiyun Li, “A novel TSV probing technique with adhesive test interposer.”,
IEEE International Conference on Computer Design (ICCD), 2015.
CCF-B [DBLP] [Scholar]
10. Yiqing Hua, Chao Li, Weichao Tang, Li Jiang, and Xiaoyao Liang, “Building Fuel Powered Supercomputing Data Center at Low Cost.”,
ACM International Conference on Supercomputing (ICS), 2015.
[DBLP] [Scholar]
11. Li Jiang and Qiang Xu, “Fault-Tolerant 3D-NoC Architecture and Design: Recent Advances and Challenges.”,
IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2015.
CSRankings [DBLP] [Scholar]
12. Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, and Qiang Xu, “On diagnosable and tunable 3D clock network design for lifetime reliability enhancement.”,
IEEE International Test Conference (ITC), 2015.
CCF-B CSRankings [DBLP] [Scholar]
13. Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, and Xinli Gu, “On test syndrome merging for reasoning-based board-level functional fault diagnosis.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.
CCF-C [DBLP] [Scholar]
14. Li Jiang and Qiang Xu, “Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist.”,
IEEE International Test Conference (ITC), 2015.
CCF-B CSRankings [DBLP] [Scholar]
15. Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, and Xinli Gu, “AgentDiag: An agent-assisted diagnostic framework for board-level functional failures.”,
IEEE International Test Conference (ITC), 2013.
CCF-B CSRankings [DBLP] [Scholar]
16. Li Jiang, Qiang Xu, and Bill Eklow, “On Effective Through-Silicon Via Repair for 3-D-Stacked ICs.”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2013.
CCF-A [DBLP] [Scholar]
17. Li Jiang, Fangming Ye, Qiang Xu, Krishnendu Chakrabarty, and Bill Eklow, “On effective and efficient in-field TSV repair for stacked 3D ICs.”,
Design Automation Conference (DAC), 2013.
CCF-A CSRankings [DBLP] [Scholar]
18. Li Jiang, Qiang Xu, Krishnendu Chakrabarty, and T. M. Mak, “Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.”,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2012.
CCF-B [DBLP] [Scholar]
19. Li Jiang, Qiang Xu, and Bill Eklow, “On effective TSV repair for 3D-stacked ICs.”,
Design, Automation and Test in Europe Conference (DATE), 2012.
CCF-B CSRankings [DBLP] [Scholar]
20. Qiang Xu, Li Jiang, Huiyun Li, and Bill Eklow, “Yield enhancement for 3D-stacked ICs: Recent advances and challenges.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2012.
CCF-C [DBLP] [Scholar]
21. Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, and Qiang Xu, “Modeling TSV open defects in 3D-stacked DRAM.”,
IEEE International Test Conference (ITC), 2010.
CCF-B CSRankings [DBLP] [Scholar]
22. Li Jiang, Rong Ye, and Qiang Xu, “Yield enhancement for 3D-stacked memory by redundancy sharing across dies.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010.
CCF-B CSRankings [DBLP] [Scholar]
23. Li Jiang, Qiang Xu, Krishnendu Chakrabarty, and T. M. Mak, “Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2009.
CCF-B CSRankings [DBLP] [Scholar]
24. Li Jiang, Lin Huang, and Qiang Xu, “Test architecture design and optimization for three-dimensional SoCs.”,
Design, Automation and Test in Europe Conference (DATE), 2009.
CCF-B CSRankings [DBLP] [Scholar]
Neuromorphic & Hyperdimensional Computing (15 formal, 8 CCF-A)
神经形态与超维计算：SNN、spiking、hyperdimensional (HDC)
1. Haomin Li, Fangxin Liu, Zongwu Wang, Ning Yang, Shiyuan Huang, Xiaoyao Liang, Haibing Guan, and
Li Jiang*, “Attack and Defense: Enhancing Robustness of Binary Hyper-Dimensional Computing.”,
ACM Transactions on Architecture and Code Optimization (ACM TACO), 2025.
CCF-A [DBLP] [Scholar]
2. Haomin Li, Fangxin Liu, Yichi Chen, Zongwu Wang, Shiyuan Huang, Ning Yang, Dongxu Lyu, and
Li Jiang*, “FATE: Boosting the Performance of Hyper-Dimensional Computing Intelligence with Flexible Numerical DAta TypE.”,
International Symposium on Computer Architecture (ISCA), 2025.
CCF-A CSRankings [DBLP] [Scholar]
3. Fangxin Liu, Haomin Li, Zongwu Wang, Dongxu Lyu, and
Li Jiang*, “HyperDyn: Dynamic Dimensional Masking for Efficient Hyper-Dimensional Computing.”,
Design, Automation and Test in Europe Conference (DATE), 2025.
CCF-B CSRankings [DBLP] [Scholar]
4. Haomin Li, Fangxin Liu, Zongwu Wang, Dongxu Lyu, Shiyuan Huang, Ning Yang, Qi Sun, Zhuoran Song, and
Li Jiang*, “TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer Parallelism.”,
Design, Automation and Test in Europe Conference (DATE), 2025.
CCF-B CSRankings [DBLP] [Scholar]
5. Ning Yang, Fangxin Liu, Zongwu Wang, Haomin Li, Zhuoran Song, Songwen Pei, and
Li Jiang*, “EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks.”,
Design Automation Conference (DAC), 2024.
CCF-A CSRankings [DBLP] [Scholar]
6. Xuan Zhang, Zhuoran Song, Peng Zhou, Xing Li, Xueyuan Liu, Xiaolong Lin, Zhezhi He, Li Jiang, Naifeng Jing, and Xiaoyao Liang, “Early: An Importance-Aware Early Firing and Exit for SNN Acceleration.”,
IEEE International Conference on Computer Design (ICCD), 2024.
CCF-B [DBLP] [Scholar]
7. Fangxin Liu, Zongwu Wang, Wenbo Zhao, Ning Yang, Yongbiao Chen, Shiyuan Huang, Haomin Li, Tao Yang, Songwen Pei, Xiaoyao Liang, and
Li Jiang*, “Exploiting Temporal-Unrolled Parallelism for Energy-Efficient SNN Acceleration.”,
IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 2024.
CCF-A [DBLP] [Scholar]
8. Haomin Li, Fangxin Liu, Yichi Chen, and
Li Jiang*, “HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
CCF-C [DBLP] [Scholar]
9. Fangxin Liu, Haomin Li, Ning Yang, Zongwu Wang, Tao Yang, and
Li Jiang*, “TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2024.
CCF-C [DBLP] [Scholar]
10. Fangxin Liu, Haomin Li, Yongbiao Chen, Tao Yang, and
Li Jiang*, “HyperAttack: An Efficient Attack Framework for HyperDimensional Computing.”,
Design Automation Conference (DAC), 2023.
CCF-A CSRankings [DBLP] [Scholar]
11. Haomin Li, Fangxin Liu, Yichi Chen, and
Li Jiang*, “HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing.”,
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2023.
CCF-B CSRankings [DBLP] [Scholar]
12. Fangxin Liu, Haomin Li, Xiaokang Yang, and
Li Jiang*, “L3E-HD: A Framework Enabling Efficient Ensemble in High-Dimensional Space for Language Tasks.”,
International ACM SIGIR Conference on Research and Development in Information Retrieval (SIGIR), 2022.
CCF-A CSRankings [DBLP] [Scholar]
13. Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, and
Li Jiang*, “SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture.”,
Design Automation Conference (DAC), 2022.
CCF-A CSRankings [DBLP] [Scholar]
14. Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, and
Li Jiang*, “SpikeConverter: An Efficient Conversion Framework Zipping the Gap between Artificial Neural Networks and Spiking Neural Networks.”,
AAAI Conference on Artificial Intelligence (AAAI), 2022.
CCF-A CSRankings [DBLP] [Scholar]
15. Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, and Xiaoyao Liang, “HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.”,
Asia and South Pacific Design Automation Conference (ASP-DAC), 2019.
CCF-C [DBLP] [Scholar]